1. Field of the Invention
The invention relates to ElectroStatic Discharge (ESD) protection for semiconductor integrated circuits (IC).
2. Background of the Invention
Integrated circuits are particularly susceptible to ElectroStatic Discharge (ESD). ESD discharges are generated by human contact, or when handling or bonding a circuit, or merely when the part is sliding around (for example when shipping the part). ESD discharge generated by human contact is modeled using the human body model described in MIL-STD 883C Method 3015.7.
ESD discharges find their way into an integrated circuit (IC) through the conductive pins (e.g. metal pins) which are connected to the pads of the IC through bond wires. In order to obtain complete immunity against transient ESD pulses, VLSI circuits must incorporate protection circuits at every input and I/O pin. The techniques for achieving this are fairly well established in the art. However, effective protection between the power supply pins are often overlooked although this is equally important for overall ESD immunity. A comprehensive method of testing requires not only the stressing of every pin with respect to V.sub.DD and Vss, but also between inputs and outputs. (C. Duvvury, R. Rountree, and O. Adams, "Internal Chip ESD Phenomena Beyond the Protection Circuit", IEEE Transactions on Electron Devices, Vol. 35, No. 12, pp. 2133-2138).
The ways of protecting a semiconductor IC from an ESD discharge depend on the function of the pin, e.g., depending on whether the pin is for input, output, or input/output (I/O) or power supply. For example, in one prior art approach, a circuit is provided near the pad that works for input pins that must present high input impedance. The same circuit may not work for output pins, I/O pins or power supply pins. Note that ESD protection circuits are often implemented near each pad on an IC, but this positioning is not necessarily required particularly in the case of power supply pins/pads.
In a prevalent general design used to protect semiconductor ICs from ESD discharge into the power supply pins, as shown in FIG. 1, an ESD protection circuit 12 is interposed between a pad 11 on IC 9, where pad 11 is coupled to a first voltage conduit 15 at Vcc and a pad 13 on IC 9, where pad 13 is coupled to a second voltage conduit 16 at Vss. Pad 11 and Pad 13 are also connected to internal circuit 14 such that internal circuit 14 is connected in parallel to ESD protection circuit 12. Voltage conduits 15 and 16 can be any one of the ground, or the power supply, or either reference voltages applied to an IC, two of them are shown as Vcc and Vss conduits. The Vss conduit is usually maintained at 0 V while the Vcc is usually maintained at 5 V however, the scheme of FIG. 1 is not intended to be limiting, as ESDs could be channeled into voltage conduits other than those at Vss and Vcc which are supplying reference voltages to an IC during the normal operation of IC 9. The function of ESD protection circuit 12 is to channel the ESD discharge from voltage conduit 15 to voltage conduit 16, while not shorting out the path from pad 11 to pad 13 when the semiconductor is powered "on" during normal semiconductor IC operation. Moreover, the ESD protection circuit must channel an ESD discharge even when the IC is powered "off" such as during ESD testing according to MIL-STD 883C Method 3015.7. It will be appreciated that pads 11 and 13 and circuits 12 and 14 are part of IC 9.
The generic ESD protection circuit 10 in FIG. 1 has been utilized in the prior art. As seen in FIG. 2, an ESD protection circuit 20 is interposed between pad 21 and pad 23 such that during an ESD discharge coming from a first voltage conduit 25 at Vcc during normal operation of the semiconductor IC when the semiconductor IC is powered "on", the current is channeled through ESD protection circuit 20 comprising an N-channel MOS transistor 27 having a gate and a drain coupled to a second voltage conduit 26, at ground, rather than being channeled through internal circuit 24. Furthermore, the current from an ESD discharge coming from a first voltage conduit 25 is also channeled through ESD protection circuit 20 when the semiconductor IC is powered "off" such that voltage conduit 25 at Vcc is floating.
When ESD protection circuit 20 is not responding to an ESD discharge channeled through voltage conduit 25, ESD protection circuit 20 is turned "off" (e.g. held in a high impedance state) such that current does not flow from the drain to a source of MQS transistor 27. But, during ESD discharge, the voltage across the drain and the source of MOS transistor 27 approaches its breakdown voltage such that MOS transistor 27 gets turned "on" (e.g. triggered into a low impedance state). When ESD protection circuit is turned "on", a sufficient amount of current flows from the drain to the source of MQS transistor 27.
As shown in FIG. 5, curve A illustrates a MOS transistor with a voltage across a gate and a source equal to 0 V, such as MOS transistor 27 in ESD protection circuit 20. According to FIG. 5, the vertical axis represents the current flowing from a drain to the source (ID) Of the MOS transistor and the horizontal axis represents the voltage across the drain and the source (V.sub.DS) of the MOS transistor. As V.sub.DS of MOS transistor 27 approaches its breakdown voltage (BV.sub.DSS(A)), MOS transistor 27 has negligible current, approximately 0 mA, flowing from the drain to the source of MOS transistor 27 shown by the horizontal portion of curve A. Once MOS transistor 27 reaches its BV.sub.DSS(A), V.sub.DS of MOS transistor 27 "snaps back" to a holding voltage (V.sub.H) of MOS transistor 27. While MOS transistor 27 is maintained at V.sub.H, MOS transistor 27 operates in its low impedance state, operating as a short circuit to allow I.sub.D to flow through ESD protection circuit 20 (thereby discharging the ESD which is causing the current I.sub.D).
The waveform of V.sub.DS of MOS transistor 27 in ESD protection circuit 20 is shown in FIG. 7. Curve V.sub.D represents the voltage across the drain and the source of the MOS transistor with the drain coupled to Vcc and the source coupled to ground. At t.sub.0, MOS transistor 27 is operating in the high impedance state while internal circuit 24 is operating under normal conditions, or more likely, voltage conduit 25 at Vcc is floating until it is "zapped" by an ESD discharge. However, the increase in V.sub.D starting at t.sub.1 represents the start of the ESD discharge through the first voltage conduit. At t.sub.2, the MOS transistor reaches BV.sub.DSS which causes V.sub.D to "snap back" to V.sub.H at t.sub.3 which is maintained until t.sub.4, at which point V.sub.D starts to decline when the ESD charge has been dissipated and MOS transistor 27 is no longer responding to the ESD discharge from the first voltage conduit.
Thus, the ESD protection device 27 controls its own operation (i.e. it is self controlling) and this self-control has been viewed as beneficial; however, this self-control has an unrecognized disadvantage. The disadvantage of allowing MOS transistor 27 to approach BV.sub.DSS (approximately 13 V in this embodiment) before snapping back to V.sub.H (approximately 7-8 V in this embodiment), is that parasitic devices directly connected across Vcc and Vss may be activated before the "snap back" is triggered at about 13 V. Once the parasitic devices are activated, they start dissipating the ESD discharge and are most likely damaged before MOS transistor 27 turns "on" to channel the ESD charge through MOS transistor 27. Examples of this damage are shown in the Duvvury reference cited.
Therefore, it is desirable to provide the ESD protection circuit 12 that operates in the low impedance state (e.g. turns "on") before the parasitic devices connected across the voltage conduits are damaged. This can be accomplished by channeling the ESD discharge through ESD protection circuit 12 before approaching the break down of the parasitic devices. In order for this to occur, the breakdown voltage of the MOS transistor must be reduced to be close to the holding voltage of the MOS transistor. The present invention provides an improved ESD protection circuit 12 that is activated upon sensing an ESD discharge and is triggered smoothly into its low impedance state before the parasitic devices are damaged.